View QL4090-1PQ208M883_1109790.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

8- 37 90,000 usable pld gate quickram combining performance, density and embedded ram military quickram rev a military quickram device highlights high performance and high density up to 90,000 usable pld gates with 316 i/os 300 mhz 16-bit counters, 400 mhz datapaths, 160+ mhz fifos 0.35um four-layer metal non-volatile cmos process for smallest die sizes high speed embedded sram up to 22 dual-port ram modules, organized in user- configurable 1,152-bit blocks 5ns access times, each port independently accessible fast and efficient for fifo, ram, and rom functions easy to use / fast development cycles 100% routable with 100% utilization and complete pin-out stability variable-grain logic cells provide high performance and 100% utilization comprehensive design tools include high quality verilog/ vhdl synthesis advanced i/o capabilities interfaces with both 3.3 volt and 5.0 volt devices pci compliant with 3.3v and 5.0v buses for -1/-2 speed grades full jtag boundary scan registered i/o cells with individually controlled clocks and output enables features total of 316 i/o pins 308 bi-directional input/output pins, pci-compliant for 5.0 volt and 3.3 volt buses for -1/-2/-3/-4 speed grades 8 high-drive input/distributed network pins eight low-skew distributed networks two array clock/control networks available to the logic cell flip-flop clock, set and reset inputs - each driven by an input-only pin six global clock/control networks available to the logic cell f1, clock, set and reset inputs and the input and i/o register clock, reset and enable inputs as well as the output enable control - each driven by an input-only or i/o pin, or any logic cell output or i/o cell feedback high performance input + logic cell + output total delays under 6 ns data path speeds exceeding 400 mhz counter speeds over 300 mhz fifo speeds over 160+ mhz military reliability mil-std-883 and miil temp ceramic mil temp plastic - guaranteed -55 c to 125 c table 1: selector table d evice h ighlights f eatures device usable gates package max i/o qualification level supply voltage ql4016 11,520 ram bits 8,000- 16,000 84cpga 84plcc 100cqfp 70 70 82 m, /883 m m, /883 3.3 v 3.3 v 3.3 v ql4036 16,128 ram bits 16,000- 25,000 144cpga 208pqfp 208cqfp 118 174 174 m, /883 m m, /883 3.3 v 3.3 v 3.3 v ql4090 25,344 ram bits 36,000- 60,000 208pqfp 208cqfp 240pqfp 256cpga 456pbga 174 174 207 223 316 m m, /883 m m, /883 m 3.3v 3.3v 3.3v 3.3v 3.3v m = military temperature (-15 to + 125 degrees c) /888 = mil std 883
38 preliminary 8-38 military quickram rev a product summary the quickram family of esps (embedded standard products) offers fpga logic in combination with dual-port sram modules. quickram is a 90,000 usable pld gate esps. quickram esps are fabri- cated on a 0.35mm four-layer metal process using quicklogic?s patented vialink technology to provide a unique combination of high performance, high density, low cost, and extreme ease-of-use. quickram contains up to 1,584 logic cells and 22 dual port ram modules. each ram module has 1,152 ram bits, for a total of up to 25,344 bits. ram modules are dual port (one read port, one write port) and can be configured into one of four modes: 64 (deep) x18 (wide), 128x9, 256x4, or 512x2. with a maximum of 316 i/os, and is avail- able in plastic 84-plcc, 208-pqfp, 240-pqfp and 456-pbga packages and in ceramic 100, 208- cqfp and 84, 144, 256-cpga. software support for the complete quickram family is available through two basic packages. the turnkey quickworks ? package provides the most complete esp software solution from design entry to logic syn- thesis, to place and route, to simulation. the quick- tools tm for workstations package provides a solution for designers who use cadence, exemplar, mentor, synopsys, synplicity, viewlogic, veribest, or other third-party tools for design entry, synthesis, or simu- lation. pinout diagram 84-pin plcc table 2: 84-pin plcc p roduct s ummary p inout d iagram 84-p in plcc quickram ql4016-1pl84m
8-39 military quickram rev a pinout diagram 100-pin cqfp 100 cqfp pinout table quickram ql4016-1cf100m pin #1 pin #76 pin #26 pin #51 p inout d iagram 100-p in cqfp 100 tqfp function 100 tqfp function 100 tqfp function 100 tqfp function 1 i/o 26 tdi 51 i/o 76 tck 2 i/o 27 i/o 52 i/o 77 stm 3 i/o 28 i/o 53 i/o 78 i/o 4 i/o 29 i/o 54 i/o 79 i/o 5 i/o 30 i/o 55 i/o 80 i/o 6 i/o 31 i/o 56 i/o 81 i/o 7 i/o 32 i/o 57 i/o 82 i/o 8 i/o 33 i/o 58 i/o 83 i/o 9 gnd 34 i/o 59 gnd 84 i/o 10 i/o 35 gnd 60 i/o 85 gnd 11 gclk / i 36 i/o 61 gclk / i 86 i/o 12 aclk / i 37 i/o 62 aclk / i 87 i/o 13 vcc 38 gnd 63 vcc 88 gnd 14 gclk / i 39 i/o 64 gclk / i 89 i/o 15 gclk / i 40 i/o 65 gclk / i 90 i/o 16 vcc 41 i/o 66 vcc 91 i/o 17 i/o 42 vccio 67 i/o 92 vccio 18 i/o 43 i/o 68 i/o 93 i/o 19 i/o 44 i/o 69 i/o 94 i/o 20 i/o 45 i/o 70 i/o 95 i/o 21 i/o 46 i/o 71 i/o 96 i/o 22 i/o 47 i/o 72 i/o 97 i/o 23 i/o 48 i/o 73 i/o 98 i/o 24 i/o 49 trstb 74 i/o 99 i/o 25 i/o 50 tms 75 i/o 100 tdo
40 preliminary 8-40 military quickram rev a 208-pin pqfp/cqfp 240-pin pqfp p inout d iagrams ql4090-1pq208m quickram pin #1 pin #157 pin #53 pin #105 quickram ql4090-1pq240m pin #1 pin #157 pin #53 pin #105
8-41 military quickram rev a pqfp/cqfp 240/208 pinout table p inout t able p inout t able 240 208 function 240 208 function 240 208 function 240 208 function 240 208 function pqfp pqfp pqfp pqfp pqfp pqfp pqfp pqfp pqfp pqfp 1 208 i/o 51 43 gnd 98 84 i/o 145 125 i/o 194 168 i/o 2 1 i/o 52 44 i/o 99 85 i/o 146 126 i/o 195 169 i/o 3 2 i/o 53 45 i/o 100 86 i/o 147 127 gnd 196 nc i/o 4 3 i/o 54 46 i/o 101 87 i/o 148 128 i/o 197 170 i/o 5 4 i/o 55 47 i/o 102 88 i/o 149 nc i/o 198 171 i/o 6 5 i/o 56 48 i/o 103 89 i/o 150 129 gclk / i 199 172 i/o 7 nc i/o 57 nc i/o 104 90 i/o 151 130 aclk / i 200 173 i/o 8 6 i/o 58 49 i/o 105 91 i/o 152 131 vcc 201 174 i/o 9 7 i/o 59 50 i/o 106 92 i/o 153 132 gclk / i 202 175 i/o 10 8 i/o 60 51 i/o 107 nc i/o 154 133 gclk / i 203 nc i/o 11 9 i/o nc 52 i/o 108 93 i/o 155 134 vcc 204 176 i/o 12 10 vcc nc 53 i/o 109 94 i/o 156 135 i/o 205 177 gnd 13 11 i/o 61 54 tdi 110 95 gnd 157 136 i/o 206 178 i/o 14 12 gnd 62 nc i/o nc 96 i/o 158 nc i/o 207 179 i/o 15 13 i/o 63 nc i/o 111 97 vcc 159 137 i/o 208 nc i/o 16 14 i/o 64 55 i/o nc 98 i/o 160 nc gnd 209 180 i/o 17 nc i/o 65 56 i/o nc 99 i/o 161 138 i/o 210 181 i/o 18 15 i/o 66 nc i/o 112 100 i/o 162 139 i/o 211 182 gnd 19 16 i/o 67 57 i/o 113 nc i/o 163 140 i/o 212 nc vcc 20 17 i/o 68 58 i/o 114 101 i/o 164 141 i/o 213 183 i/o 21 18 i/o 69 59 gnd 115 nc i/o 165 142 i/o 214 184 i/o 22 19 i/o 70 60 i/o 116 102 i/o 166 nc i/o 215 185 i/o 23 20 i/o 71 61 vcc 117 nc i/o 167 143 i/o 216 186 i/o 24 nc i/o 72 62 i/o 118 nc i/o 168 144 i/o 217 187 vccio 25 21 i/o 73 63 i/o 119 103 trstb 169 145 vcc 218 188 i/o 26 22 i/o 74 64 i/o 120 104 tms 170 nc i/o 219 nc i/o 27 23 gnd 75 nc i/o 121 105 i/o 171 146 i/o 220 189 i/o 28 24 i/o 76 65 i/o 122 nc i/o 172 147 gnd 221 190 i/o 29 25 gclk / i 77 66 i/o 123 106 i/o 173 148 i/o 222 191 i/o 30 26 aclk / i 78 67 i/o 124 107 i/o 174 149 i/o 223 192 i/o 31 27 vcc 79 nc i/o 125 108 i/o 175 150 i/o 224 193 i/o 32 28 gclk / i 80 68 i/o 126 109 i/o 176 151 i/o 225 194 i/o 33 29 gclk / i 81 69 i/o 127 nc i/o 177 152 i/o 226 nc i/o 34 30 vcc 82 70 i/o 128 110 i/o 178 153 i/o 227 195 i/o 35 31 i/o 83 nc i/o 129 111 i/o 179 154 i/o 228 196 i/o 36 32 i/o nc 71 i/o 130 112 i/o 180 155 i/o 229 197 i/o 37 nc gnd 84 nc i/o 131 113 i/o nc 156 i/o 230 198 i/o 38 33 i/o 85 72 i/o 132 114 vcc 181 157 tck 231 nc i/o 39 nc i/o 86 73 gnd 133 115 i/o 182 158 stm 232 199 gnd 40 34 i/o 87 74 i/o 134 116 gnd 183 nc i/o 233 200 i/o 41 35 i/o 88 nc vcc 135 117 i/o 184 159 i/o 234 201 vcc 42 36 i/o 89 75 i/o 136 nc i/o 185 160 i/o 235 202 i/o 43 nc i/o 90 76 i/o 137 118 i/o 186 161 i/o 236 203 i/o 44 37 i/o 91 77 i/o 138 119 i/o 187 162 i/o 237 204 i/o 45 38 i/o 92 78 gnd 139 120 i/o 188 163 gnd 238 205 i/o 46 39 i/o 93 79 i/o 140 121 i/o 189 164 i/o 239 206 i/o 47 nc i/o 94 80 i/o 141 nc i/o 190 165 vcc 240 207 tdo 48 40 i/o 95 81 i/o 142 122 i/o 191 166 i/o 49 41 vcc 96 82 i/o 143 123 i/o 192 nc i/o 50 42 i/o 97 83 vccio 144 124 i/o 193 167 i/o
42 preliminary 8-42 military quickram rev a pinout diagram 84-pin cpga 84-pin cpga pinout table p inout d iagram 84-p in cpga 84 cpga function 84 cpga function 84 cpga function 84 cpga function a1 i/o b11 i/o f9 i/o k2 i/o a2 i/o c1 vcc f10 i/o k3 i/o a3 i/o c2 i/o f11 i/o k4 i/o a4 i/o c5 vcc g1 i/o k5 gclk / i a5 i/o c6 aclk / i g2 i/o k6 gclk / i a6 i/o c7 gnd g3 vccio k7 gclk / i a7 i/o c10 i/o g9 gnd k8 i/o a8 i/o c11 i/o g10 i/o k9 i/o a9 i/o d1 i/o g11 i/o k10 tck a10 i/o d2 i/o h1 i/o k11 i/o a11 tdo d10 i/o h2 i/o l1 tms b1 i/o d11 i/o h10 vcc l2 i/o b2 tdi e1 i/o h11 i/o l3 i/o b3 i/o e2 i/o j1 i/o l4 i/o b4 i/o e3 gnd j2 trstb l5 i/o b5 gclk / i e9 vccio j5 gnd l6 i/o b6 gclk / i e10 i/o j6 aclk / i l7 i/o b7 gclk / i e11 i/o j7 vcc l8 i/o b8 i/o f1 i/o j10 stm l9 i/o b9 i/o f2 i/o j11 i/o l10 i/o b10 i/o f3 i/o k1 i/o l11 i/o quickram ql4016-1cg84m
8-43 military quickram rev a pinout diagrams 144 & 256-pin cpgas 144-pin cpga 256-pin cpga p inout d iagrams 144 & 256-p in cpga s quickram ql4036-1cg144m 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 y w v u t r p n m l k j h g f e d c b a quickram ql4090-1cg256m
44 preliminary 8-44 military quickram rev a pinout table 144-pin cpga p inout t able 144-p in cpga 144 cpga function 144 cpga function 144 cpga function 144 cpga function a1 i/o c7 i/o h13 aclk / i n10 i/o a2 i/o c8 gnd h14 i/o n11 gnd a3 i/o c9 i/o h15 gclk / i n12 i/o a4 i/o c10 i/o j1 gclk / i n13 i/o a5 i/o c11 i/o j2 vcc n14 i/o a6 i/o c12 tck j3 vcc n15 i/o a7 i/o c13 i/o j13 i/o p1 i/o a8 i/o c14 i/o j14 i/o p2 i/o a9 i/o c15 i/o j15 gnd p3 tdi a10 gnd d1 i/o k1 gclk / i p4 i/o a11 i/o d2 i/o k2 i/o p5 i/o a12 i/o d3 i/o k3 i/o p6 i/o a13 vcc d13 i/o k13 i/o p7 i/o a14 i/o d14 i/o k14 i/o p8 i/o a15 i/o d15 i/o k15 i/o p9 vccio b1 i/o e1 i/o l1 i/o p10 i/o b2 tdo e2 vcc l2 i/o p11 i/o b3 i/o e3 i/o l3 gnd p12 i/o b4 i/o e13 gnd l13 i/o p13 i/o b5 i/o e14 i/o l14 vcc p14 trstb b6 i/o e15 i/o l15 i/o p15 i/o b7 vccio f1 i/o m1 i/o r1 i/o b8 i/o f2 i/o m2 i/o r2 i/o b9 i/o f3 i/o m3 i/o r3 vcc b10 i/o f13 i/o m13 i/o r4 i/o b11 i/o f14 i/o m14 i/o r5 i/o b12 i/o f15 gclk / i m15 i/o r6 gnd b13 stm g1 gnd n1 i/o r7 i/o b14 i/o g2 i/o n2 i/o r8 i/o b15 i/o g3 i/o n3 i/o r9 i/o c1 i/o g13 vcc n4 i/o r10 i/o c2 i/o g14 vcc n5 i/o r11 i/o c3 i/o g15 gclk / i n6 i/o r12 i/o c4 i/o h1 gclk / i n7 i/o r13 i/o c5 gnd h2 i/o n8 gnd r14 i/o c6 i/o h3 aclk / i n9 i/o r15 tms
8-45 military quickram rev a pinout table 256-pin cpga 256 cpga function 256 cpga function 256 cpga function 256 cpga function 256 cpga function 256 cpga function a1 vcc c4 i/o e19 i/o l2 gclk / i t17 i/o v20 i/o a2 i/o c5 i/o e20 vcc l3 gnd t18 i/o w1 i/o a3 vcc c6 i/o f1 i/o l4 i/o t19 i/o w2 i/o a4 i/o c7 i/o f2 gnd l17 gclk / i t20 i/o w3 i/o a5 i/o c8 i/o f3 i/o l18 i/o u1 i/o w4 i/o a6 i/o c9 i/o f4 i/o l19 vcc u2 i/o w5 gnd a7 i/o c10 i/o f17 i/o l20 aclk / i u3 i/o w6 i/o a8 i/o c11 vcc f18 gnd m1 vcc u4 i/o w7 i/o a9 i/o c12 i/o f19 i/o m2 i/o u5 i/o w8 i/o a10 gnd c13 i/o f20 i/o m3 i/o u6 i/o w9 i/o a11 i/o c14 i/o g1 i/o m4 i/o u7 i/o w10 i/o a12 i/o c15 i/o g2 i/o m17 i/o u8 i/o w11 gnd a13 i/o c16 i/o g3 i/o m18 i/o u9 i/o w12 i/o a14 i/o c17 i/o g4 i/o m19 i/o u10 vcc w13 vccio a15 i/o c18 i/o g17 i/o m20 i/o u11 i/o w14 i/o a16 i/o c19 i/o g18 i/o n1 i/o u12 i/o w15 i/o a17 i/o c20 i/o g19 i/o n2 i/o u13 i/o w16 i/o a18 gnd d1 vcc g20 i/o n3 i/o u14 i/o w17 i/o a19 i/o d2 i/o h1 i/o n4 i/o u15 i/o w18 i/o a20 tck d3 i/o h2 i/o n17 i/o u16 i/o w19 trstb b1 i/o d4 i/o h3 i/o n18 i/o u17 i/o w20 i/o b2 i/o d5 i/o h4 i/o n19 i/o u18 i/o y1 tdi b3 i/o d6 i/o h17 i/o n20 gnd u19 i/o y2 i/o b4 gnd d7 i/o h18 i/o p1 i/o u20 i/o y3 i/o b5 i/o d8 i/o h19 i/o p2 i/o v1 i/o y4 vcc b6 i/o d9 i/o h20 i/o p3 vcc v2 i/o y5 i/o b7 i/o d10 i/o j1 i/o p4 i/o v3 i/o y6 i/o b8 vccio d11 i/o j2 i/o p17 gnd v4 i/o y7 i/o b9 i/o d12 i/o j3 gnd p18 i/o v5 i/o y8 i/o b10 vcc d13 i/o j4 i/o p19 i/o v6 i/o y9 i/o b11 i/o d14 i/o j17 i/o p20 i/o v7 i/o y10 i/o b12 gnd d15 i/o j18 vcc r1 i/o v8 i/o y11 i/o b13 i/o d16 i/o j19 gnd r2 i/o v9 vcc y12 i/o b14 i/o d17 stm j20 vcc r3 gnd v10 gnd y13 i/o b15 i/o d18 i/o k1 aclk / i r4 i/o v11 i/o y14 i/o b16 vcc d19 i/o k2 vcc r17 i/o v12 i/o y15 i/o b17 i/o d20 i/o k3 gnd r18 vcc v13 i/o y16 i/o b18 gnd e1 i/o k4 gclk / i r19 i/o v14 i/o y17 vcc b19 i/o e2 i/o k17 i/o r20 i/o v15 gnd y18 i/o b20 i/o e3 i/o k18 i/o t1 i/o v16 i/o y19 i/o c1 i/o e4 i/o k19 gclk / i t2 i/o v17 gnd y20 i/o c2 i/o e17 i/o k20 gclk / i t3 i/o v18 tms c3 tdo e18 i/o l1 gclk / i t4 vcc v19 i/o p inout t able 256-p in cpga
46 preliminary 8-46 military quickram rev a pinout diagram 456-pin pbga 456 pin pbga top bottom p inout d iagram 456-p in pbga ql4090-1pb456c quickram m pin a1 corner
8-47 military quickram rev a pinout table 456-pin pbga (cont ? d on next page) p inout t able 456-p in pbga 456 function 456 function 456 function 456 function 456 function a1 i/o b26 stm d25 i/o h4 i/o m14 gnd/therm a2 i/o c1 i/o d26 i/o h5 nc m15 gnd/therm a3 i/o c2 i/o e1 i/o h22 nc m16 gnd/therm a4 i/o c3 i/o e2 i/o h23 i/o m22 nc a5 i/o c4 tdo e3 i/o h24 i/o m23 nc a6 i/o c5 i/o e4 i/o h25 i/o m24 i/o a7 i/o c6 i/o e5 gnd h26 i/o m25 i/o a8 i/o c7 i/o e6 vcc j1 i/o m26 i/o a9 i/o c8 i/o e7 gnd j2 i/o n1 gclk/i a10 i/o c9 i/o e8 nc j3 i/o n2 i/o a11 i/o c10 i/o e9 gnd j4 nc n3 i/o a12 vccio c11 i/o e10 i/o j5 gnd n4 gclk/i a13 i/o c12 i/o e11 gnd j22 nc n5 vcc a14 i/o c13 i/o e12 gnd j23 nc n11 gnd/therm a15 i/o c14 i/o e13 vcc j24 i/o n12 gnd/therm a16 i/o c15 i/o e14 gnd j25 i/o n13 gnd/therm a17 i/o c16 i/o e15 gnd j26 i/o n14 gnd/therm a18 i/o c17 i/o e16 gnd k1 i/o n15 gnd/therm a19 i/o c18 i/o e17 nc k2 i/o n16 gnd/therm a20 i/o c19 i/o e18 gnd k3 i/o n22 gnd a21 i/o c20 i/o e19 nc k4 i/o n23 i/o a22 i/o c21 i/o e20 gnd k5 vcc n24 i/o a23 i/o c22 i/o e21 vcc k22 gnd n25 i/o a24 i/o c23 i/o e22 gnd k23 i/o n26 i/o a25 i/o c24 i/o e23 i/o k24 i/o p1 i/o a26 i/o c25 tck e24 i/o k25 i/o p2 i/o b1 i/o c26 i/o e25 i/o k26 i/o p3 i/o b2 i/o d1 i/o e26 i/o l1 i/o p4 i/o b3 i/o d2 i/o f1 i/o l2 i/o p5 nc b4 i/o d3 i/o f2 i/o l3 i/o p11 gnd/therm b5 i/o d4 gnd f3 i/o l4 i/o p12 gnd/therm b6 i/o d5 i/o f4 nc l5 nc p13 gnd/therm b7 i/o d6 nc f5 vcc l11 gnd/therm p14 gnd/therm b8 i/o d7 i/o f22 vcc l12 gnd/therm p15 gnd/therm b9 i/o d8 i/o f23 nc l13 gnd/therm p16 gnd/therm b10 i/o d9 gnd f24 i/o l14 gnd/therm p22 nc b11 i/o d10 i/o f25 i/o l15 gnd/therm p23 gclk / i b12 i/o d11 i/o f26 i/o l16 gnd/therm p24 gclk / i b13 i/o d12 gnd g1 i/o l22 nc p25 i/o b14 i/o d13 i/o g2 i/o l23 i/o p26 aclk / i b15 i/o d14 i/o g3 i/o l24 i/o r1 i/o b16 i/o d15 gnd g4 i/o l25 i/o r2 i/o b17 i/o d16 i/o g5 nc l26 i/o r3 i/o b18 i/o d17 i/o g22 gnd m1 aclk / i r4 nc b19 i/o d18 gnd g23 i/o m2 gclk/i r5 nc b20 i/o d19 i/o g24 i/o m3 i/o r11 gnd/therm b21 i/o d20 i/o g25 i/o m4 nc r12 gnd/therm b22 i/o d21 nc g26 i/o m5 gnd r13 gnd/therm b23 i/o d22 i/o h1 i/o m11 gnd/therm r14 gnd/therm b24 i/o d23 gnd h2 i/o m12 gnd/therm r15 gnd/therm b25 i/o d24 i/o h3 i/o m13 gnd/therm r16 gnd/therm
48 preliminary 8-48 military quickram rev a pbga 456 pinout table (continued from previous page) 456 function 456 function 456 function 456 function r22 vcc y1 i/o ac6 nc ae5 i/o r23 nc y2 i/o ac7 i/o ae6 i/o r24 i/o y3 i/o ac8 i/o ae7 i/o r25 i/o y4 i/o ac9 nc ae8 i/o r26 gclk / i y5 i/o ac10 i/o ae9 i/o t1 i/o y22 gnd ac11 i/o ae10 i/o t2 i/o y23 i/o ac12 nc ae11 i/o t3 i/o y24 i/o ac13 i/o ae12 i/o t4 i/o y25 i/o ac14 vccio ae13 i/o t5 vcc y26 i/o ac15 nc ae14 i/o t11 gnd/thermal aa1 i/o ac16 i/o ae15 i/o t12 gnd/thermal aa2 i/o ac17 i/o ae16 i/o t13 gnd/thermal aa3 nc ac18 nc ae17 i/o t14 gnd/thermal aa4 nc ac19 i/o ae18 i/o t15 gnd/thermal aa5 vcc ac20 i/o ae19 i/o t16 gnd/thermal aa22 vcc ac21 i/o ae20 i/o t22 gnd aa23 nc ac22 nc ae21 i/o t23 i/o aa24 i/o ac23 gnd ae22 i/o t24 i/o aa25 i/o ac24 i/o ae23 nc t25 i/o aa26 i/o ac25 i/o ae24 tms t26 i/o ab1 i/o ac26 i/o ae25 i/o u1 i/o ab2 i/o ad1 i/o ae26 i/o u2 i/o ab3 i/o ad2 nc af1 i/o u3 i/o ab4 i/o ad3 i/o af2 i/o u4 i/o ab5 gnd ad4 i/o af3 i/o u5 gnd ab6 vcc ad5 i/o af4 i/o u22 nc ab7 nc ad6 i/o af5 i/o u23 i/o ab8 nc ad7 i/o af6 i/o u24 i/o ab9 nc ad8 i/o af7 i/o u25 i/o ab10 vcc ad9 i/o af8 i/o u26 i/o ab11 gnd ad10 i/o af9 i/o v1 i/o ab12 nc ad11 i/o af10 i/o v2 i/o ab13 i/o ad12 i/o af11 i/o v3 i/o ab14 gnd ad13 i/o af12 i/o v4 nc ab15 vcc ad14 i/o af13 i/o v5 nc ab16 i/o ad15 i/o af14 i/o v22 gnd ab17 nc ad16 i/o af15 i/o v23 nc ab18 vcc ad17 i/o af16 i/o v24 i/o ab19 gnd ad18 i/o af17 i/o v25 i/o ab20 nc ad19 i/o af18 i/o v26 i/o ab21 vcc ad20 i/o af19 i/o w1 i/o ab22 gnd ad21 i/o af20 i/o w2 i/o ab23 i/o ad22 i/o af21 i/o w3 i/o ab24 i/o ad23 trstb af22 i/o w4 i/o ab25 i/o ad24 i/o af23 i/o w5 nc ab26 i/o ad25 i/o af24 i/o w22 nc ac1 i/o ad26 i/o af25 i/o w23 i/o ac2 i/o ae1 tdi af26 i/o w24 i/o ac3 nc ae2 i/o w25 i/o ac4 gnd ae3 i/o w26 i/o ac5 i/o ae4 i/o
8-49 military quickram rev a pin descriptions ordering information p in d escriptions pin function description tdi/rsi test data in for jtag / ram init. serial data in hold high during normal operation. connects to serial prom data in for ram initialization. connect to vcc if unused. trstb/rro active low reset for jtag / ram init. reset out hold low during normal operation. connects to serial prom reset for ram initialization. connect to gnd if unused. tms test mode select for jtag hold high during normal operation. connect to vcc if not used for jtag. tck test clock for jtag hold high or low during normal operation. connect to vcc or ground if not used for jtag. tdo/rco test data out for jtag / ram init. clock out connect to serial prom clock for ram initialization. must be left unconnected if not used for jtag or ram initialization. stm special test mode must be grounded during normal operation. i/aclk high-drive input and/or array network driver can be configured as either or both. i/gclk high-drive input and/or global network driver can be configured as either or both. i high-drive input use for input signals with high fanout. i/o input/output pin can be configured as an input and/or output. vcc power supply pin connect to 3.3v supply. vccio input voltage tolerance pin connect to 5.0 volt supply if 5 volt input tolerance is required, otherwise connect to 3.3v supply. gnd ground pin connect to ground. gnd/therm ground/thermal pin available on 456-pbga only. connect to ground plane on pcb if heat sinking desired. otherwise may be left unconnected. ql 4090 - 1 pq208 m operating range m = military m/883 = mil std 883 package code pl84 = 84-pin plcc cg84=84-pin cpga cf100 = 100-pin cqfp cg144=144-pin cpga pq208 = 208-pin pqfp cf208 = 208-pin cqfp pq240 = 240-pin pqfp cg256=256-pin cpga cg456=456-pin pbga quicklogic device quickram device part number 4016 4036 4090 speed grade 0 = quick 1 = fast 2 = faster
50 preliminary 8-50 military quickram rev a absolute maximum ratings vcc voltage ...........................-0.5 to 4.6v vccio voltage .......................-0.5 to 7.0v input voltage.............. -0.5 to vccio+0.5v latch-up immunity ...................200 ma dc input current ...................... 20 ma esd pad protection .................... 2000v storage temperature .......-65 c to +150 c lead temperature ...........................300 c operating range dc characteristics notes: [1] military devices have 8 ma iol specifications. [2] capacitance is sample tested only. clock pins are 12 pf maximum. [3] only one output at a time. duration should not exceed 30 seconds. [4] maximum icc is 5 ma for all military grade devices. for ac conditions, contact quicklogic customer engineering. symbol parameter military unit min max vcc supply voltage 3.0 3.6 v vccio i/o input tolerance voltage 3.0 5.5 v ta ambient temperature -55 c tc case temperature 125 c -0 speed grade 0.42 2.03 k delay factor -1 speed grade 0.42 1.64 -2 speed grade 0.42 1.37 symbol parameter conditions min max unit vih input high voltage 0.5vcc vccio+0.5 v vil input low voltage -0.5 0.3vcc v voh output high voltage ioh = -12 ma 2.4 v ioh = -500 a 0.9vcc v vol output low voltage iol = 8 ma [1] 0.45 v iol = 1.5 ma 0.1vcc v ii i or i/o input leakage current vi = vccio or gnd -10 10 a ioz 3-state output leakage current vi = vccio or gnd -10 10 a ci input capacitance [2] 10 pf ios output short circuit current [3] vo = gnd -15 -180 ma vo = vcc 40 210 ma icc d.c. supply current [4] vi, vio = vccio or gnd 0.50 (typ) 5 ma iccio d.c. supply current on vccio 0 100 a
8-51 military quickram rev a ql4016 ac characteristics at vcc = 3.3v, ta = 25 c (k = 1.00) (to calculate delays, multiply the appropriate k factor in the "operating range" section by the following numbers.) logic cells input-only/clock cells notes: [6] stated timing for worst case propagation delay over process variation at vcc=3.3v and ta=25 c. multiply by the appropriate delay factor, k, for speed grade, voltage and temperature settings as speci- fied in the operating range. [7] these limits are derived from a representative selection of the slowest paths through the quickram logic cell including typical net delays. worst case delay values for specific paths should be determined from timing analysis of your particular design. ql4016 symbol parameter propagation delays (ns) fanout [6] 12348 tpd combinatorial delay [7] 1.4 1.7 1.9 2.2 3.2 tsu setup time [7] 1.7 1.7 1.7 1.7 1.7 th hold time 0.0 0.0 0.0 0.0 0.0 tclk clock to q delay 0.7 1.0 1.2 1.5 2.5 tcwhi clock high time 1.2 1.2 1.2 1.2 1.2 tcwlo clock low time 1.2 1.2 1.2 1.2 1.2 tset set delay 1.0 1.3 1.5 1.8 2.8 treset reset delay 0.8 1.1 1.3 1.6 2.6 tsw set width 1.9 1.9 1.9 1.9 1.9 trw reset width 1.8 1.8 1.8 1.8 1.8 symbol parameter propagation delays (ns) fanout [6] 123481224 tin high drive input delay 1.5 1.6 1.8 1.9 2.4 2.9 4.4 tini high drive input, inverting delay 1.6 1.7 1.9 2.0 2.5 3.0 4.5 tisu input register set-up time 3.1 3.1 3.1 3.1 3.1 3.1 3.1 tih input register hold time 0.0 0.0 0.0 0.0 0.0 0.0 0.0 tlclk input register clock to q 0.7 0.8 1.0 1.1 1.6 2.1 3.6 tlrst input register reset delay 0.6 0.7 0.9 1.0 1.5 2.0 3.5 tlesu input register clock enable setup time 2.3 2.3 2.3 2.3 2.3 2.3 2.3 tleh input register clock enable hold time 0.0 0.0 0.0 0.0 0.0 0.0 0.0
52 preliminary 8-52 military quickram rev a ql4016 clock cells i/o cell input delays i/o cell output delays notes: [6] stated timing for worst case propagation delay over process variation at vcc=3.3v and ta=25 c. multiply by the appropriate delay factor, k, for speed grade, voltage and temperature settings as specified in the operating range. [8] the array distributed networks consist of 40 half columns and the global distributed networks consist of 44 half columns, each driven by an independent buffer. the number of half columns used does not affect clock buffer delay. the array clock has up to 8 loads per half column. the global clock has up to 11 loads per half column. [9] the following loads are used for tpxz: symbol parameter propagation delays (ns) loads per half column [8] 123481011 tack array clock delay 1.2 1.2 1.3 1.3 1.5 1.6 1.7 tgckp global clock pin delay 0.7 0.7 0.7 0.7 0.7 0.7 0.7 tgckb global clock buffer delay 0.8 0.8 0.9 0.9 1.1 1.2 1.3 symbol parameter propagation delays (ns) fanout [6] 1234810 ti/o input delay (bidirectional pad) 1.3 1.6 1.8 2.1 3.1 3.6 tisu input register set-up time 3.1 3.1 3.1 3.1 3.1 3.1 tih input register hold time 0.0 0.0 0.0 0.0 0.0 0.0 tloclk input register clock to q 0.7 1.0 1.2 1.5 2.5 3.0 tlorst input register reset delay 0.6 0.9 1.1 1.4 2.4 2.9 tlesu input register clock enable set-up time 2.3 2.3 2.3 2.3 2.3 2.3 tleh input register clock enable hold time 0.0 0.0 0.0 0.0 0.0 0.0 symbol parameter propagation delays (ns) output load capacitance (pf) 30 50 75 100 150 toutlh output delay low to high 2.1 2.5 3.1 3.6 4.7 touthl output delay high to low 2.2 2.6 3.2 3.7 4.8 tpzh output delay tri-state to high 1.2 1.7 2.2 2.8 3.9 tpzl output delay tri-state to low 1.6 2.0 2.6 3.1 4.2 tphz output delay high to tri-state [9] 2.0 tplz output delay low to tri-state [9] 1.2 5 pf 1k ? 5 pf 1k ? tphz tplz
8-53 military quickram rev a ql4036 ac characteristics at vcc = 3.3v, ta = 25 c (k = 1.00) (to calculate delays, multiply the appropriate k factor in the "operating range" section by the following numbers.) logic cells input-only/clock cells notes: [5] stated timing for worst case propagation delay over process variation at vcc=3.3v and ta=25 c. multi- ply by the appropriate delay factor, k, for speed grade, voltage and temperature settings as specified in the operating range. [6] these limits are derived from a representative selection of the slowest paths through the pasic 3 logic cell including typical net delays. worst case delay values for specific paths should be determined fromtiming analysis of your particular design. ql4036 symbol parameter propagation delays (ns) fanout [5] 12348 tpd combinatorial delay [6] 1.4 1.7 1.9 2.2 3.2 tsu setup time [6] 1.7 1.7 1.7 1.7 1.7 th hold time 0.0 0.0 0.0 0.0 0.0 tclk clock to q delay 0.7 1.0 1.2 1.5 2.5 tcwhi clock high time 1.2 1.2 1.2 1.2 1.2 tcwlo clock low time 1.2 1.2 1.2 1.2 1.2 tset set delay 1.0 1.3 1.5 1.8 2.8 treset reset delay 0.8 1.1 1.3 1.6 2.6 tsw set width 1.9 1.9 1.9 1.9 1.9 trw reset width 1.8 1.8 1.8 1.8 1.8 symbol parameter propagation delays (ns) fanout [5] 123481224 tin high drive input delay 1.5 1.6 1.8 1.9 2.4 2.9 4.4 tini high drive input, inverting delay 1.6 1.7 1.9 2.0 2.5 3.0 4.5 tisu input register set-up time 3.1 3.1 3.1 3.1 3.1 3.1 3.1 tih input register hold time 0.0 0.0 0.0 0.0 0.0 0.0 0.0 tlclk input register clock to q 0.7 0.8 1.0 1.1 1.6 2.1 3.6 tlrst input register reset delay 0.6 0.7 0.9 1.0 1.5 2.0 3.5 tlesu input register clock enable setup time 2.3 2.3 2.3 2.3 2.3 2.3 2.3 tleh input register clock enable hold time 0.0 0.0 0.0 0.0 0.0 0.0 0.0
54 preliminary 8-54 military quickram rev a ql4036 clock cells i/o cell input delays i/o cell output delays notes: [5] stated timing for worst case propagation delay over process variation at vcc=3.3v and ta=25 c. multiply by the appropriate delay factor, k, for speed grade, voltage and temperature settings as specified in the operating range. [7] the array distributed networks consist of 56 half columns and the global distributed networks consist of 60 half columns, each driven by an independent buffer. the number of half columns used does not affect clock buffer delay. the array clock has up to 12 loads per half column. the global clock has up to 15 loads per half column. [8] the following loads are used for tpxz: symbol parameter propagation delays (ns) loads per half column [7] 12348101215 tack array clock delay 1.2 1.2 1.3 1.3 1.5 1.6 1.7 1.8 tgckp global clock pin delay 0.7 0.7 0.7 0.7 0.7 0.7 0.7 0.7 tgckb global clock buffer delay 0.8 0.8 0.9 0.9 1.1 1.2 1.3 1.4 symbol parameter propagation delays (ns) fanout [5] 1234810 ti/o input delay (bidirectional pad) 1.3 1.6 1.8 2.1 3.1 3.6 tisu input register set-up time 3.1 3.1 3.1 3.1 3.1 3.1 tih input register hold time 0.0 0.0 0.0 0.0 0.0 0.0 tloclk input register clock to q 0.7 1.0 1.2 1.5 2.5 3.0 tlorst input register reset delay 0.6 0.9 1.1 1.4 2.4 2.9 tlesu input register clock enable set-up time 2.3 2.3 2.3 2.3 2.3 2.3 tleh input register clock enable hold time 0.0 0.0 0.0 0.0 0.0 0.0 symbol parameter propagation delays (ns) output load capacitance (pf) 30 50 75 100 150 toutlh output delay low to high 2.1 2.5 3.1 3.6 4.7 touthl output delay high to low 2.2 2.6 3.2 3.7 4.8 tpzh output delay tri-state to high 1.2 1.7 2.2 2.8 3.9 tpzl output delay tri-state to low 1.6 2.0 2.6 3.1 4.2 tphz output delay high to tri-state [8] 2.0 tplz output delay low to tri-state [8] 1.2 5 pf 1k ? 5 pf 1k ? tphz tplz
8-55 military quickram rev a ql4090 ac characteristics at vcc = 3.3v, ta = 25 c (k = 1.00) (to calculate delays, multiply the appropriate k factor in the "operating range" section by the following numbers.) logic cells input-only/clock cells notes: [5] stated timing for worst case propagation delay over process variation at vcc=3.3v and ta=25 c. multiply by the appropriate delay factor, k, for speed grade, voltage and temperature settings as specified in the operating range. [6] these limits are derived from a representative selection of the slowest paths through the pasic 3 logic cell including typical net delays. worst case delay values for specific paths should be determined from timing analysis of your particular design. ql4090 symbol parameter propagation delays (ns) fanout [5] 12348 tpd combinatorial delay [6] 1.4 1.7 1.9 2.2 3.2 tsu setup time [6] 1.7 1.7 1.7 1.7 1.7 th hold time 0.0 0.0 0.0 0.0 0.0 tclk clock to q delay 0.7 1.0 1.2 1.5 2.5 tcwhi clock high time 1.2 1.2 1.2 1.2 1.2 tcwlo clock low time 1.2 1.2 1.2 1.2 1.2 tset set delay 1.0 1.3 1.5 1.8 2.8 treset reset delay 0.8 1.1 1.3 1.6 2.6 tsw set width 1.9 1.9 1.9 1.9 1.9 trw reset width 1.8 1.8 1.8 1.8 1.8 symbol parameter propagation delays (ns) fanout [5] 123481224 tin high drive input delay 1.5 1.6 1.8 1.9 2.4 2.9 4.4 tini high drive input, inverting delay 1.6 1.7 1.9 2.0 2.5 3.0 4.5 tisu input register set-up time 3.1 3.1 3.1 3.1 3.1 3.1 3.1 tih input register hold time 0.0 0.0 0.0 0.0 0.0 0.0 0.0 tlclk input register clock to q 0.7 0.8 1.0 1.1 1.6 2.1 3.6 tlrst input register reset delay 0.6 0.7 0.9 1.0 1.5 2.0 3.5 tlesu input register clock enable setup time 2.3 2.3 2.3 2.3 2.3 2.3 2.3 tleh input register clock enable hold time 0.0 0.0 0.0 0.0 0.0 0.0 0.0
56 preliminary 8-56 military quickram rev a ql4090 clock cells i/o cell input delays i/o cell output delays notes: [5] stated timing for worst case propagation delay over process variation at vcc=3.3v and ta=25 c. multiply by the appropriate delay factor, k, for speed grade, voltage and temperature settings as spec- ified in the operating range. [7] the array distributed networks consist of 88 half columns and the global distributed networks consist of 92 half columns, each driven by an independent buffer. the number of half columns used does not affect clock buffer delay. the array clock has up to 18 loads per half column. the global clock has up to 20 loads per half column. [8] the following loads are used for tpxz: symbol parameter propagation delays (ns) loads per half column [7] 1 2 3 4 8 10 12 14 16 18 20 tack array clock delay 1.2 1.2 1.3 1.3 1.5 1.6 1.7 1.8 1.9 2 2.1 tgckp global clock pin delay 0.7 0.7 0.7 0.7 0.7 0.7 0.7 0.7 0.7 0.7 0.7 tgckb global clock buffer delay 0.8 0.8 0.9 0.9 1.1 1.2 1.3 1.4 1.5 1.6 1.7 symbol parameter propagation delays (ns) fanout [5] 1234810 ti/o input delay (bidirectional pad) 1.3 1.6 1.8 2.1 3.1 3.6 tisu input register set-up time 3.1 3.1 3.1 3.1 3.1 3.1 tih input register hold time 0.0 0.0 0.0 0.0 0.0 0.0 tloclk input register clock to q 0.7 1.0 1.2 1.5 2.5 3.0 tlorst input register reset delay 0.6 0.9 1.1 1.4 2.4 2.9 tlesu input register clock enable set-up time 2.3 2.3 2.3 2.3 2.3 2.3 tleh input register clock enable hold time 0.0 0.0 0.0 0.0 0.0 0.0 symbol parameter propagation delays (ns) output load capacitance (pf) 30 50 75 100 150 toutlh output delay low to high 2.1 2.5 3.1 3.6 4.7 touthl output delay high to low 2.2 2.6 3.2 3.7 4.8 tpzh output delay tri-state to high 1.2 1.7 2.2 2.8 3.9 tpzl output delay tri-state to low 1.6 2.0 2.6 3.1 4.2 tphz output delay high to tri-state [8] 2.0 tplz output delay low to tri-state [8] 1.2 5 pf 1k ? 5 pf 1k ? tphz tplz
8-57 military quickram rev a ram cell synchronous write timing ram cell synchronous read timing ram cell asynchronous read timing notes: [5] stated timing for worst case propagation delay over process variation at vcc=3.3v and ta=25 c. multiply by the appropriate delay factor, k, for speed grade, voltage and temperature settings as specified in the operating range. symbol parameter propagation delays (ns) fanout 12348 tswa wa setup time to wclk 1.0 1.0 1.0 1.0 1.0 thwa wa hold time to wclk 0.0 0.0 0.0 0.0 0.0 tswd wd setup time to wclk 1.0 1.0 1.0 1.0 1.0 thwd wd hold time to wclk 0.0 0.0 0.0 0.0 0.0 tswe we setup time to wclk 1.0 1.0 1.0 1.0 1.0 thwe we hold time to wclk 0.0 0.0 0.0 0.0 0.0 twcrd wclk to rd (wa=ra) [5] 5.0 5.3 5.6 5.9 7.1 symbol parameter propagation delays (ns) fanout 12348 tsra ra setup time to rclk 1.0 1.0 1.0 1.0 1.0 thra ra hold time to rclk 0.0 0.0 0.0 0.0 0.0 tsre re setup time to rclk 1.0 1.0 1.0 1.0 1.0 thre re hold time to rclk 0.0 0.0 0.0 0.0 0.0 trcrd rclk to rd [5] 4.0 4.3 4.6 4.9 6.1 symbol parameter propagation delays (ns) fanout 12348 rpdrd ra to rd [5] 3.0 3.3 3.6 3.9 5.1
58 preliminary 8-58 military quickram rev a

▲Up To Search▲

Price & Availability of QL4090-1PQ208M883

	To Download QL4090-1PQ208M883 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .